The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to a recessed channel CMOS device that has low series resistance and improved short-channel characteristics. The present invention also relates to a method of fabricating such a recessed channel CMOS device.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
In recent years, and as channel lengths are being scaled below 0.1 xcexcm, SOI complementary metal oxide semiconductor (CMOS) technology has received considerable interest in VLSI for its potential low-voltage, low-power, and high-speed advantages in comparison to bulk CMOS devices. As known to those skilled in the art, SOI structures include an insulating layer, i.e., buried oxide region (BOX), that electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing, i.e., the SOI layer, serves as the area in which electronic devices such as CMOS devices can be fabricated.
Thin film SOI CMOS devices, such as SOI MOSFETs, in which the top Si-containing layer has a thickness of about 20 nm or less, are of special interest due to improved isolation, reduced parasitic capacitance as well as the reduction of short-channel and floating body effects that can be obtained from such technology. Despite the known advantages with thin film SOI technology, processing challenges exist which substantially hamper the use of thin SOI MOSFETs in semiconductor integrated circuits. For example, prior art processes for fabricating OI MOSFETs have difficulty in forming a thin (20 nm or less) SOI channel region. One prior art technique to obtain very thin SOI channels is to recess the channel while protecting the S/D regions. This prior art technique ensures that the series resistance of the device can be kept small since the S/D regions can be made as thick as desired. However, in existing recessed channel technology, it is difficult to form extension and halo implant regions having abrupt, i.e., sharp, lateral profiles that overlap the gate edges.
In view of the above-mentioned drawbacks with fabricating prior art thin SOI MOSFETs, there exists a need for providing a new and improved method for fabricating recessed channel MOSFETs which have a thin SOI device channel region as well as adjoining extension and halo implant regions havirig abrupt lateral profiles that overlap the edges of the gate region.
One object of the present invention is to provide a high-performance recessed channel CMOS device.
Another object of the present invention is to provide a recessed channel CMOS device in which the short-channel effects and series resistance have been substantially minimized.
A further object of the present invention is to provide a recessed channel CMOS device in which the external resistance of the device is not substantially degraded.
A yet further object of the present invention is to provide a recessed channel CMOS device in which the extension implant regions adjoining the recessed channel have an abrupt lateral profile. The term xe2x80x9cabrupt lateral profilexe2x80x9d as used herein for extension implant regions denotes a lateral drop of 1 decade in concentration in 50 xc3x85 or less distance for n-extensions and 150 xc3x85 or less for p-extensions.
An even further object of the present invention is to provide a recessed channel CMOS device in which the extension implant regions overlap the edges of the gate region.
A still even further object of the present invention is to provide a recessed channel CMOS device in which the halo implant regions have an abrupt lateral profile. For halo implant regions, the term xe2x80x9cabrupt lateral profilexe2x80x9d denotes a lateral drop of 1 decade in concentration in 700 xc3x85 or less distance for n-halos and in 400 xc3x85 or less for p-halos.
These and other objects and advantages are achieved in the present invention by utilizing a method wherein disposable, i.e., sacrificial, spacers are present during the fabrication of the recessed channel and the source/drain regions, but are removed just prior to formation of the extension implant regions. This ensures that the extension implant regions as well as the halo implant regions have an abrupt lateral profile that extends beneath the edges of the gate region of the MOSFET device.
Specifically, and in one aspect of the present invention, a recessed channel CMOS device is provided. In accordance with this aspect of the present invention the recessed channel CMOS device comprises:
an SOI layer having a recessed channel region and adjoining extension implant regions; and
at least one gate region present atop said SOI layer, wherein said adjoining extension implant regions have an abrupt lateral profile and are located beneath said gate region.
The inventive device may optionally include adjoining halo implant regions that also have an abrupt lateral profile that extends beneath the edges of the gate region.
Another aspect of the present invention relates to a method of fabricating the above-mentioned recessed channel CMOS device. Specifically, the method of the present invention comprises the step of:
providing a patterned oxide layer over an SOI layer, said patterned oxide layer exposing a portion of said SOI layer;
thinning the exposed portion of the SOI layer to form a recessed channel region;
forming a gate dielectric on said recessed channel region;
forming sacrificial nitride spacers on portions of said gate dielectric so as to protect exposed walls of said SOI layer and said oxide layer and forming a gate conductor on other portions of the gate dielectric not containing said sacrificial nitride spacers;
recessing the oxide layer exposing SOI layer abutting the recessed channel region;
forming source/drain diffusion regions in said exposed SOI layer abutting the recessed channel region; and
removing the sacrificial nitride spacers and forming extension and optional halo implant regions in said SOI layer such that said extension and optional halo implant regions have an abrupt lateral profile and are located beneath the gate conductor.
After the extension implant regions are formed, the inventive method further includes forming insulator spacers on exposed sidewalls of the gate conductor.